| 摘要 |
PURPOSE:To recognize an abnormality of the input pulse data and to avoid the wrong control without giving load to a CPU by detecting the abnormality of the pulse data after deciding the coincidence between the number of pulses obtained when a prescribed period of time passed and the prescribed number of pulses. CONSTITUTION:An interface counter part 9 delivers the first input pulse to a controller 111 of a microprocessor 11. The controller 111 receives the first pulse and sets a timer 112 under an enable state. Thus the timer 112 is started and reads the pulse data out of the part 9 after a prescribed timer time (t). The number of pulses of said pulse data is compared with the preset data (six pulses) set previously in a memory part 113. If no coincidence is obtained from said comparison, the controller 111 delivers the abnormality data and an interruption signal to a CPU13 via an input/output bus 14. The CPU13 receives the abnormality data and recognizes the abnormality of the pulse data supplied from a sensor 8.
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