| 摘要 |
PURPOSE:To vary potential on the inversion layer side of memory capacitance constituted of an inversion layer and a common electrode for memory cells intentionally, and to prevent a leakage to a bit line of charges stored in the memory capacitance of the memory cells by giving the potential of the common electrode by a clock. CONSTITUTION:A common electrode 2 is connected to a power supply terminal 7 by clock pulses CP1 on reading and writing, and stable potential is obtained. When reading and writing cycles are completed, the clock pulses CP1 are brought to a low level and a transistor 10 is interrupted while clock pulses CP2 are brought to a high level and the potential of the common electrode 2 is made higher than supply voltage by a capacitance 11. The potential of an inversion layer 4 is also elevated by the operation, and a transfer transistor TG is not conducted, thus resulting in no leakage to a bit line 5 of electrons in the inversion layer 4 in a memory cell. Accordingly, the lowering of the SN ratio of a reading signal can be obviated, thus realizing high performance of the device.
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