| 摘要 |
PURPOSE:To obtain a testing circuit reduced at the number of elements by enabling individual adders to be simultaneously tested, using terminals to be used at a normal mode as I/O terminals necessary for these tests in common and switching the terminals at a test mode. CONSTITUTION:In the test mode, I/O terminals A, B in the normal operation mode are used in common and latch circuits 1-7 enter data as shift registers. The test mode is released only by one pitch and the circuits 1-7 are operated as latches. consequently, adders 8-10 input data latched by the latches 1-6 respectively to add these data. The added results are latched by the latches 5-7. After the latch of these data, the operation mode is turned to the test mode again and the circuits 1-7 are operated as the shift registers again. Consequently, the latches 5-7 output the operated results from the circuits 8-10 to serial terminals C-E respectively. Therefore, the terminals C-E and the test mode switching terminals can be used in common. |
