发明名称 Dynamic memory with improved arrangement for precharging bit lines.
摘要 <p>@ A dynamic memory which can precharge a pair of bit lines accurately to a potential of half a power voltage and has an improved detection characteristics of data read-out is disclosed. The dynamic memory is of the type that a precharge potential of a pair of bit lines is generated by short-circuiting the pair of bit lines after the pair of bit lines are discriminated into the power voltage and a reference voltage. A compensation capacitor is provided for the pair of bit lines. The compensation capacitor is charged to the power voltage and the charged compensation capacitor is operatively connected to the pair of bit lines when they are short-circuited thereby to raise the potential on the bit lines to half the power voltage.</p>
申请公布号 EP0189908(A2) 申请公布日期 1986.08.06
申请号 EP19860101143 申请日期 1986.01.29
申请人 NEC CORPORATION 发明人 MUROTANI, TATSUNORI
分类号 G11C11/409;G11C11/4094 主分类号 G11C11/409
代理机构 代理人
主权项
地址