| 摘要 |
PURPOSE:To reduce the number of high-speed gates to reduce power consumption by transmitting O/H bits a disital repeating signal to the output of a shift register by a low-speed timing signal. CONSTITUTION:The digital repeating signal including an O/H bit signal and a synchronizing signal is held successively in the shift register consisting of flip flops F/F1-F/FN by input clocks. An output Q' of each stage of the shift register is connected to a synchronous detecting circuit 11 and is subjected to synchronous detection. O/H bit information is held in the shift register after synchronous detection, and information is sent to a data output terminal by low-speed clocks, which are switched from clocks supplied to the shift register by a selecting circuit 14 consisting of agates and are supplied from a timing circuit 12, before the following synchronizing bit is inputted to a data terminal D of the flip flop F/F1.
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