| 摘要 |
<p>Undesired current flow in a CMOS driver circuit (31) is minimized or eliminated during the portion of the switching interval when both transistors (42, 43) are conducting. The p-MOS and the n-MOS transistors (33, 34) in the CMOS inverter switching circuit (30) coupled to the gates of the driver CMOS (31) are interconnected through CMOS transistors (36, 37) which are continuously biased on. During switching, a voltage is developed across these CMOS transistors (36, 37) which delays turn-on of the non-conducting driver CMOS transistor (42 or 43) until the current in the complementary driver transistor (43 or 42) is reduced to a low value or to zero. This invention relates to CMOS transistor circuitry in which parasitic current flow during switching of the transistor is minimized or eliminated.</p> |
