发明名称 Address translation buffer control system
摘要 A computer virtual memory system having a translation lookaside buffer (TLB) in which the result of a dynamic address translation system is stored when in a normal mode or when a non-privileged instruction is executed, but the result is not stored when in a privileged mode or when a privileged instruction is executed, such as a storage key operation. The storage does not occur even though the effective address of the privileged instruction is translated into a physical address.
申请公布号 US4604688(A) 申请公布日期 1986.08.05
申请号 US19830509868 申请日期 1983.06.30
申请人 FUJITSU LIMITED 发明人 TONE, HIROSADA
分类号 G06F12/10;G06F12/14;(IPC1-7):G06F12/10 主分类号 G06F12/10
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