发明名称 ADDRESS CONVERSION BUFFER CONTROL SYSTEM IN MULTIPLE VIRTUAL MEMORY SYSTEM
摘要 PURPOSE:To regard multiway bits as obstruction to make efficient use of ILB by removing the possibility of multiway bits at the time of reading when the common segment bit CS of new data registered in an address conversion buffer TLB is '1'. CONSTITUTION:Logical addresses of '1' of a CS bit register 6 of the new conversion data is registered in buffers 1, 2 of a multiple virtual memory system. During registering, the logical address of a logical address register 3, a space identification number register 5, the logical register LA of the buffers 1 and 2, and space identification number STO are compard in comparators 7-10. If there are ways 0, 1 that concide upon such comparison, they are registered in the respective ways 0, 1 by using CS of new conversion data. In case of concurrent coincidence, one of them is registered in one and the other is invalidated. In case there is no coincidence in any ways, the way to be registered is determined by Least Recently Used method by a register way determining circuit 40.
申请公布号 JPS61173359(A) 申请公布日期 1986.08.05
申请号 JP19850014721 申请日期 1985.01.29
申请人 FUJITSU LTD 发明人 MORI TSUYOSHI
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
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