发明名称 METHOD FOR RECOGNITION OF IDLE WIRING RANGE
摘要 PURPOSE:To reduce the designing time of wiring pattern by providing a table for storing the number of patterns present in each lattice obtained by dividing the surface of a printed plate and referring with the table to discriminated the possibility of wiring. CONSTITUTION:A pattern number table 12 is provided in a memory device 1. In the table 2 the pattern number (n) of pattern numbers present in each lattice X, Y is stored on the print plate. A processing device 3 for studying the arrangement of new wiring patterns Pi extracts from the designing data of the pattern Pi a row X (for example, C) which is the object of installment and then extracts the starting row Ys of a pattern Pi (such as b) and an end rop Ye (such as f). Then the device 3 initializes the row Y in the row Ys, refers with a pattern number table 2 in the device 1, extracts the pattern number (n) of the lattices X, Y and compares it when an upper limit n0. When the condition n<n0 holds upu to a row Y=f it is judged that the wiring is possible for the pattern Pi. When the condition n<n0 (n0 is 2) does not hold as lattice X, Y=B, d then it is judged that the wiring is impossible.
申请公布号 JPS61173384(A) 申请公布日期 1986.08.05
申请号 JP19850014720 申请日期 1985.01.29
申请人 FUJITSU LTD 发明人 YAMAGUCHI TAKAO
分类号 H05K3/00;G06F17/50 主分类号 H05K3/00
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