Decimal arithmetic logic unit for doubling or complementing decimal operand

摘要

A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is an arithmetic logic unit (ALU) that functions with the CPU. The ALU has operand inputs to which are connected switched steering circuits that permit particular operands and zero operands to be selectively applied to any or all of the ALU operand inputs. This allows easy performance of special arithmetic functions such as adding a decimal operand to itself when converting the decimal operand to a binary operand, and to subtract a decimal operand from zero when complementing decimal operands.