| 摘要 |
PURPOSE:To dispense with means for synchronizing system clocks and enable signals by producing enable signals used in ICs for peripheral circuit by system clocks of a mi microprocessor. CONSTITUTION:By the inputting of system clocks phi from a system clock oscillator 3, signals from input/output demand terminal iORQ' of CPU1 and signals from write instruction terminal WR' are transmitted. Negative logic NAND11 signal are inputted into an a ddress decoder 10 and an IC2. In short, an address data inputted into the address decoder and a siganl i'/ow' is decoded 10, a signal is inputted to a chip selector CS' terminal of IC2, and a binary counter 5 is cleared. When the output terminals QA, QB of the counter 5 are high by clocks phi, the output from an AND circuit 8 goes high to clear the counter 5. The signals from terminals QA, QB goes low so taht the output from an OR circuit 7 and enable signal E are also low. |
