| 摘要 |
PURPOSE:To reduce the parasitic capacitance by a method wherein semiconductor films and gate insulation films are formed at the same time, the latter of which is removed except the gate region, and the contact for source-drain electrodes is formed there. CONSTITUTION:Amorphous hydrogenated Si films a-Si(I) 4, an Na-Si 14, an Si nitride Sin 3, and an N<+> a-Si 13 are successively deposited on a glass substrate 1, and a Cr film 6 is deposited thereon and processed by photo etching. The Cr is plasma-etched with CF4 at part of the a-Si and SiN by means of a solution of ceric ammonium nitrate. Next, the SiN is etched down to the N-type a-SiN 14. With a photo resist 15 remaining, an N<+> a-Si 5 and Cr-Al electrodes for source-rain electrodes are formed thereon, and the a-Si 5, Cr, and Al in the unnecessary part are etched away. This system can contrive the reduction in parasitic capacitance by self-alignment. |
