发明名称 INFORMATION PROCESSING CONTROLLER IN MULTIPLEX TRANSMISSION SYSTEM
摘要 PURPOSE:To prevent malrecognition of information due to a time shift in a duplex system by providing the two sets of buffer memories to the transmission interface of an outgoing system in the duplex transmission system of incoming/outgoing system so as to select an instruction having the highest priority. CONSTITUTION:A central control section A consists of duplex computers 11a, 11b, a supervisory controller 13 and interfaces IFs 12a, 12b, 14a, 14b and is connected to a common bus 15. The bus 15 is connected to a switch section 19 via duplex transmission sections B1-Bn as the incoming and outgoing systems. A controlled section C comprised of plural controlled stations 20 is connected to the switch section 19. Two sets of buffer memories are provided to the IF16a of the outgoing system of the transmission sections B, write a control output from the controller 13 to the two sets of the memories, the stored contents are compared and an instruction to be executed with the highest priority is selected. A command from the other If is made ineffective during the transmission from the control section A to the transmission sections B as a busy state, the information is informed to the other IF at the end of transmission and a new control command is given to the other IF section by the information.
申请公布号 JPS61171251(A) 申请公布日期 1986.08.01
申请号 JP19850011945 申请日期 1985.01.25
申请人 JAPANESE NATIONAL RAILWAYS<JNR>;MEIDENSHA ELECTRIC MFG CO LTD 发明人 FUKADA NARIYUKI;KAWABE KOICHI;KURIMOTO TAKATSUGU
分类号 H04Q9/00 主分类号 H04Q9/00
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