发明名称 EXPANSION SYSTEM OF MICROPROCESSOR INSTRUCTION
摘要 PURPOSE:To reduce the capacity of memory to be used sharply by using a specific instruction as an expanded instruction. CONSTITUTION:When the instruction is read from an objective program storing means 101 to a microprocessor 100, the instruction is decoded by a logic circuit in a physical instruction analyzing means 106. The decoded signal is decomposed to a signal corresponding to the instruction and the signal is executed by an instruction executing means 107 except restart. A signal 122 is obtained by decoding a restart instruction which is the 1st byte of expanded instructions and executed by a restart executing means 108 and then the address of an expanded instruction analyzing means 103 is set up in an address register 109. The means 103 analyzes the 2nd byte of the expanded instructions. A return address setting means 104 decides the instruction length of the expanded instructions and sets up the leading address of the instruction next to the expanded instructions on the objective program as a return address and an expanded instruction executing means 105 executes the expanded instructions analyzed by the means 103.
申请公布号 JPS61169937(A) 申请公布日期 1986.07.31
申请号 JP19850010122 申请日期 1985.01.23
申请人 NEC CORP 发明人 MIKOJIMA HIROO
分类号 G06F9/30 主分类号 G06F9/30
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