发明名称 LOGICAL CIRCUIT
摘要 PURPOSE:To prevent the transition time of an output potential from a low potential to high potential from being increased by providing a circuit lowering a base potential of a transistor (TR) when a potential at a common terminal is decreased to a negative potential in a high drive capability output buffer circuit provided with a phase split TR between the base and the common terminal of the TR. CONSTITUTION:A base potential control circuit 10 is provided between an input terminal 1 and the common terminal 5. The base potential control circuit 10 has a TRQ5 provided with a Schottky clamp diode and other TRQ6. Then the emitter of the TRQ6 and the base of the TRQ6 are connected and the collector of the TRQ5 and the collector of the TRQ6 are connected to constitute a Darlington connection circuit. When the common terminal 6 is at a negative potential (<=-0.4V) momentarily on the way of the input signal potential at the input terminal 1 inverted from a low potential L to a high potential H, the potential difference between the terminal 2 and the common terminal 5 is increased to decrease the potential at the input terminal 1. Thus, the TRQ1, Q2 are not turned on and then the transition time is not increased.
申请公布号 JPS61170127(A) 申请公布日期 1986.07.31
申请号 JP19850010133 申请日期 1985.01.23
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 SONODA MOTOI
分类号 H03K19/088;H03K17/04;H03K19/013 主分类号 H03K19/088
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