| 摘要 |
PURPOSE:To reduce the difference of the dispersion of element shapes and characteristics between both P and N channel MOS transistors by controlling the length of channels formed under gate electrodes so as to be equalized between both P and N channel MOS transistors. CONSTITUTION:An silicon oxide layer 16 is formed onto the surface of a polycrystalline silicon layer 12, and a polycrystalline oxide on the surface of a P well on the left side is removed through wet etching while masking a region on the right side. A structure 10 is exposed into the atmosphere of POCl3 to thermally diffuse P into a polycrystalline silicon layer 14 in a region on the left side. The ions of P or As are implanted to the main surface of the structure 10. The quantity of P or As doped into the region, in which an N channel is shaped, on the left side is made larger than that in the region, in which a P channel is formed, on the right side, and P or As into the region on the left side is not activated. Masks 18 are shaped, and the surface is plasma-etched. |
