发明名称 POWER-ON CLEAR CIRCUIT
摘要 PURPOSE:To prevent an error signal from being outputted to a noise after application of power by utilizing a different transistor (TR) depending on application of power and after power-on to produce a sure rest signal at application of power. CONSTITUTION:A capacitor 8 and a resistive TR1 are connected in series between power supplies, an inverter 4 is connected from the midpoint, its output is connected in cascade to inverters 5-7 and the output of the inverter 7 is a reset signal for clearing power-on. At application of power, the TR1 is turned on, a TR2 is turned off,and in the steady-state after application of power conversely, the TR1 is turned off and the TR2 is turned on. Thus, the constant of the TR1 is decided to obtain a sufficient pulse width as a reset pulse and the on-resistance of the TR2 is decreased to improve the stability of the closed loop. Further, in order to improve the stability of the closed loop at the steady- state, the transition point of the inverter 4 is biased positively.
申请公布号 JPS61170123(A) 申请公布日期 1986.07.31
申请号 JP19850010244 申请日期 1985.01.23
申请人 SEIKO EPSON CORP 发明人 KOBAYASHI HAJIME;KODAIRA MITSUHARU;HAYASHI KENJI
分类号 H03K17/22 主分类号 H03K17/22
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