| 摘要 |
A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected to divide the high voltage (+V) substantially equally across the P channel transistors, when the P channel transistors are turned off, and substantially evenly divide the high voltage across the N channel transistors, when the N channel transistors are turned off. In another embodiment of this invention, selected ones of the N channel and P channel transistors are formed in order to have a high drain to bulk breakdown voltage. In another embodiment of this invention, a plurality of N channel and a plurality of P channel transistors are connected in series and driven by a single ended control voltage (CN), thus providing a first stage (101) which drives a second stage (100) having a plurality of P channel transistors and a plurality of N channel transistors (110, 111, 112), which provide the high voltage output voltage. In another embodiment of this invention, the first stage (101) is driven by a single ended control voltage (CN) and serves to drive a second stage (103) comprising a plurality of N channel transistors (110, 111, 112) and a plurality of bipolar transistors (120, 121), whereby said second stage provides the high voltage output signal. |
