发明名称 A ratioless FET programmable logic array.
摘要 <p>A ratioless, zero d.c. power dissipating FET programmable logic array including a column boost capacitor for maintaining the columns of selected AND array transistors at approximately their precharged voltage while their associated OR array transistors are being evaluated.</p>
申请公布号 EP0188834(A2) 申请公布日期 1986.07.30
申请号 EP19850201979 申请日期 1985.11.27
申请人 N.V. PHILIPS' GLOEILAMPENFABRIEKEN 发明人 MAHMUD, SYED TAYYEB
分类号 H03K19/177;H03K19/20;(IPC1-7):H03K19/177;H03K19/017 主分类号 H03K19/177
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