| 摘要 |
PURPOSE:To shorten the processing time and access time of a memory access controller, by transmitting the response of a main storage device to the 2nd MM (main memory) responding circuit and BUS responding circuit when a flag indicating that a peripheral control device is high in performance is on. CONSTITUTION:The access time of a memory access controller is made higher in performance irrespectively of a preceding access request in such a way that, when access requests from peripheral control devices 13-16 are accepted, the content of a flag displaying that one of the peripheral control devices 13-16 is high in performance is stored until the response of a main storage device 10 is obtained and the 'on' or 'off' of the flag is read when the main storage device 10 responds. When the flag is 'on', the response of the main storage device 10 is transmitted to the 2nd main storage responding circuit 31 and to a bus responding circuit 36 and the response from the main storage device is received separately from the response to a preceding access request, and then, the response from the main storage device is returned to the peripheral control device prior to the response to the preceding access request.
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