发明名称 |
Method for composing addresses of a memory |
摘要 |
A method for subdividing the addresses of a multi-dimensional memory, having n-dimensional addresses defined over a logical address space which is divided into a plurality of unit divisions. Each unit division has several vertices each of which is addressable by one of the n-dimensional addresses. Each one of the addresses associated with a given unit division is divided and allocated to a distinct memory bank so that no two addresses of the same unit division are in the same memory bank. There are a total of 2n memory banks, each having independent data lines and address lines. The original n-dimensional address of the vertices determines to which memory bank the vertex address will be allocated. Moreover, the n-dimensional address also determines the address of the given vertex within the memory bank to which it has been allocated. Thus, the data corresponding to all the vertices of a given unit division can be accessed simultaneously to thereby significantly reduce data retrieval times in many applications.
|
申请公布号 |
US4603348(A) |
申请公布日期 |
1986.07.29 |
申请号 |
US19830460286 |
申请日期 |
1983.01.24 |
申请人 |
DAINIPPON SCREEN SEIZO KABUSHIKI KAISHA |
发明人 |
YAMADA, MITSUHIKO;NISHIDA, TSUKASA;INOUE, TOSHIFUMI |
分类号 |
G11C7/00;G06F12/06;G06T1/60;G11C8/00;(IPC1-7):H04N1/46 |
主分类号 |
G11C7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|