| 摘要 |
PURPOSE:To obtain a static type storage circuit which has a high response speed without increasing the chip area by varying the P-N junction capacity of some of memory cells arranged in a matrix of plural rows and columns. CONSTITUTION:The matrix array consists of storage cells Ekj, digit line load elements LkN, decoding output word lines W1K, digit line couples Dk1 and Dk2, digit signal transfer gates Qk1 and Qk2, digit selection lines Y1k, data lines D10 and D20, and reference potential V00(V701) and V01(V702). Each storage cell E have load elements L701 and L702, drivers Q701 and Q702, and transfer gates Q703 and Q704 connected as specified and a potential V1101 lower than a reference potential V702 is applied during reading operation. At this time, transfer gates Q703 and Q704 formed in the N well of a P substrate are applied with the V1101 at an electrode 807 to reduce the junction capacity and increase the response speed. Therefore, the Q703 and Q704 need not be increased in size for speed improvement and there is no increase in chip area. |
