| 摘要 |
PURPOSE:To reduce the overhead time required by bus switching, by controlling the bus switching in such a way that, when an access request is made from a peripheral LSI side, a resource memory can be connected with the peripheral LSI side until the access disappears. CONSTITUTION:Under conditions where a resource bus 3b is connected with a system bus 3c because of a DMA transferring request, changeover controlling signals SEL1 and SEL2 do not change immediately during the period when a status signal BBSY stays high in level, even when an access requesting signal ASBU from the system bus 3c side falls at every transfer of each word. Moreover, even when an access request is made from an MPU1, the MPU1 is a waited. After one-block transfer is terminated and the status signal BBSY changes to a low level, the changeover controlling signal SEL1 is changed to a high level and the signal SEL2 is to a low level, respectively. As a result, an MPU bus 3a is connected with the resource bus 3b instead of the system bus 3c and access from the MPU1 becomes possible. |
