发明名称 PROCESSING SYSTEM FOR ADDRESS CONVERSION ERROR
摘要 PURPOSE:To process errors, etc. with high efficiency by comparing an access code with a memory protection code in case an error is detected with a conversion buffer, etc. and at the same time using a buffer invalid flag and an address conversion exception flag. CONSTITUTION:When no coincidence is obtained between a memory protection code and an access code given from an MPU1, an error signal is delivered if an access is impossible after having comparison 9 between both said codes. Then a buffer invalid flag 11 is set when the buffer invalid bit V of the data read out of an address conversion buffer 3 is equal to '1'. Then the access of an access destination device is suppressed and a sub-MPU2 is started. This MPU2 produces a physical address corresponding to a logical address delivered from the MPU1 and performs a writing action to a buffer 3 to reset the flag 11. Then the retrieval is given to a segment table, etc. for production of a physical address. Under such conditions, and address conversion exception flag 12 and a control flag 13 are set with the flag 11 reset respectively as long as an invalid page, etc. are detected.
申请公布号 JPS61166653(A) 申请公布日期 1986.07.28
申请号 JP19850008077 申请日期 1985.01.19
申请人 PANAFACOM LTD 发明人 IKEDA KAZUHIKO;KOIZUMI NAOKI
分类号 G06F11/00;G06F12/10;G06F12/14 主分类号 G06F11/00
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