| 摘要 |
PURPOSE:To obtain an output signal converted into an 8-bit speed from a position of a synchronizing signal independently of a frequency of a high-speed clock by forming a 2-1 selection circuit controlled by a load signal and a latch circuit connected in cascade with the selection circuit to form a parallel/serial converting circuit. CONSTITUTION:A signal from the inside of a load signal generating circuit 14-2 of a control signal generating circuit 14 stops a counter at a prescribed value, the content is decoded to generate a load signal. Since a 2-1 selection circuit 15-2 or the like controlled by the said load signal and a latch circuit 15-1 or the like connected in cascade with the said 2-1 selection circuit form a parallel/serial converting circuit 15, an output signal subjected to speed conversion in an 8-bit from the location of the synchronizing signal is obtained independently of the high-speed clock frequency. |
