MULTI-PROCESSOR CONTROL SYSTEM

摘要

PURPOSE:To inhibit temporarily the wiring action of a processor at the other side to a shared memory means by supplying the logical arithmetic output of a wiring permission flag corresponding to the read/write signal of another processor to a write control terminal of a memory means. CONSTITUTION:In a normal mode the values of an FF9-A and FF9-B are set at 1 and microprocessors 1-A and 1-B deliver the writing requests of a memory means 2. Thus 0 is supplied to a write terminal in the i-hh and (i+1)-th time bands. Then data are written to the means 2 by th processor 1-A in the i-th time band. While the processor 1-B writes data to the means in the (i+1)-th time band. When the values of the FF9-A and FF9-B are equal to 1 and 0 respectively, 0 is supplied to the write terminal in the i-th time band. Thus the processor 1-A can write data and the writing action of the processor 1-B is inhibited since 1 is supplied in the (i+1)-th time band. Thus it is possible to inhibit temporarily the writing of data to the means 2 from a processor at the other side through a simple constitution.