| 摘要 |
<p>PURPOSE:To prevent a reading mistake of data by fixing the level of a non- selected data line and furthermore to shorten the access time by setting the fixed level at an intermediate level of the data line. CONSTITUTION:Data lines D0-Dn are connected to a bias voltage generating circuit via EMOSTs Q0-Qn, and signals -Y0-Yn obtained by inverting the input signals Y0-Yn of a Y gate are supplied to the gates of EMOSTs Q0-Qn respectively. If the data line D0, for example, is selected, the EMOST0 connected to the line D0 is turned off. Then the line D0 is separated from the bias generating circuit and the level of the line D0 is equal to a specific level that is decided by the contents of the data on either one of selected memory cell transistors Q00-Qmn. While the EMOSTQn connected to the non-selected data line Dn, for example, is turned on. Then the line Dn is fixed at the level given from the bias generating circuit.</p> |
