| 摘要 |
<p>PURPOSE:To enable to operate at a high speed, by making low concentration source or drain regions below near gate electrodes in non volatile memory elements coupled to the data line, by operating this semiconductor regions as sources to do write operation, and by operating it as drains to do read operation. CONSTITUTION:FAMOS transistors Q1-Q6 have semiconductor regions coupled to the data line, being low concentration below near the gates, in order to improve writing efficiency and reading speed. In the writing operation, selected FAMOS transistors have semiconductor regions coupled to the data line, acted as sources, and have semiconductor regions coupled to the common source-drain line CSD, acted as drains. Moreover, in the reading operation, outputs of inverter circuits IV1 and IV2 are made a low level such as the circuit ground potential owing to a program controlling signal PGM being high level. Accordingly, the common source-drain line CSD is made a low level such as the circuit ground potential.</p> |
