发明名称 BUFFER ACCESS REQUEST CONTROLLING SYSTEM
摘要 PURPOSE:To shorten a delay caused by a competition, by informing a fact that the competition can be generated, to an instruction control part, and stopping a progress of a state of a pipeline for a time of one control cycle. CONSTITUTION:In case a write processing which is reinputted from a stage B4 and a new request of a control line 1 have competed with each other, a stage P2 does not receive the new request but sends a signal for informing a fact that the write processing exists by a control line 30, to an instruction control part 12. When the signal of the control line 30 is received, the instruction control part 12 locks a state of a pipe line, and holds the present state until the next cycle. Unless a write processing request exists in the next cycle, the new request is executed.
申请公布号 JPS61165136(A) 申请公布日期 1986.07.25
申请号 JP19840276324 申请日期 1984.12.28
申请人 FUJITSU LTD 发明人 ONISHI KATSUMI;OINAGA YUJI
分类号 G06F9/38;G06F12/08 主分类号 G06F9/38
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