发明名称 INTERRUPTION CONTROLLING SYSTEM
摘要 PURPOSE:To simplify an interruption processing in each CPU by setting a bit corresponding to the logical equipment item number concerned of an interruption register in the CPU through a common bus by using a specified command, when an interrupting request has been generated in a channel processor. CONSTITUTION:When an interrupting request is generated in one of channel processors (CH), for instance, CHi, a specified command is issued through a common bus 4, only a bus line corresponding to the logical equipment item number of the channel processor concerned CHi in a data bus of the common bus 4 is energized, and the bit concerned of an interruption register 12 in a CPU0 and a CPU1 is turned on. The CPU0 or the CPU1 starts an interruption processing by the contents of its interruption register 12, namely, the contents of an interruption mask register provided in accordance with the interruption register concerned 12, and instructs an interrupting operation to said CHi by the specified command through the common bus 4.
申请公布号 JPS61165168(A) 申请公布日期 1986.07.25
申请号 JP19840270439 申请日期 1984.12.21
申请人 FUJITSU LTD 发明人 KOYABU MASAO
分类号 G06F13/24;(IPC1-7):G06F13/24 主分类号 G06F13/24
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