| 摘要 |
PURPOSE:To effectively suppress the generation of a latch-up phenomenon by a method wherein an N<+> type contact region to be connected to power source voltage and a P<+> type contact region to be connected to the earth poten tial VSS are arranged on the semiconductor substrate located between the source regions of two MOS transistors and a P-type well region respectively. CONSTITUTION:A P-channel MOS transistor 5, consisting of P<+> type source and drain regions 2 and 3 and a gate electrode, is formed on an N-type semicon ductor substrate 1, and an N<+> type source and drain regions 7 and 8 and an N-channel MOS transistor 10, consisting of a gate electrode 9, are formed on a P-type well region 6. An N<+> type first contact region 11 and a P<+> type second contact region 12 are formed on the semiconductor substrate 1 located between the source regions 2 and 7 of transistors 5 and 10 and the well region 6 respec tively. As the PNP transistor 14, constituting the holding loop of latch-up, and an NPN transistor 15 ar turned to non-conductive state, the latch-up phenome non can be easily prevented. |
