| 摘要 |
PURPOSE:To synthesize efficiently two adjacent frequency components by setting an electric length of a transmission line so that input waves which have been divided equally into two paths from other input terminal, respectively, on an interface of an input terminal become a roughly opposite phase to each other, and the output becomes zero. CONSTITUTION:A component which has been inputted from an input terminal 1 is divided into two in an interface A, and a phase of the component which passes through a circulator 11 and reaches an interface B, of said two components is delayed by (1/4+n12)lambda based on the interface A as a reference. On the other hand, a phase of the component which phases through an interface C and a circulator 12 from the interface A, and reaches the interface B is delayed by (1/4+n13+n32+1/2)lambda based on the interface A as a reference. Said two components become an opposite phase to each other in the interface B, therefore, they are not outputted to an input terminal 2. On the other hand, a phase of the component which passes through the circulator 11, the interface B and the circulator 12 from the interface A, and reaches the interface C is delayed by (1/4+n12+n23)lambda based on the interface A as a reference, but a phase of the component which reaches the interface C directly from the interface A becomes (1/4+n13)lambda based on the interface A as a reference, and these two components become the same phase and are outputted to an output terminal 3. That is to say, all input waves from the input terminal 1 are outputted to the output terminal 3. |
