发明名称 CIRCUIT ARRANGEMENT FOR REGISTER
摘要 A circuit arrangement for use in an integrated circuit having a built-in self test design, the circuit arrangement comprising first and second gates coupled to a flip-flop via a third gate. The present invention provides a multiplexer coupled to one input of the first gate, the multiplexer being controllable by a control signal to feed either input data or output data of the circuit arrangement to said one input of the first gate and a fourth gate coupled to an input of the second gate, the fourth gate having an input connected to receive a signal dependent on the control signal to the data selector means.
申请公布号 AU5148085(A) 申请公布日期 1986.07.24
申请号 AU19850051480 申请日期 1985.12.19
申请人 PLESSEY OVERSEAS LTD. 发明人 DAVID FRANK BURROWS;MARK PARASKEVA;WILLIAM LAWRENCE KNIGHT
分类号 G01R31/28;G01R31/3185 主分类号 G01R31/28
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