发明名称 EMITTER-COUPLED LOGIC CIRCUIT
摘要 An emitter-coupled logic (ECL) circuit having a pull-down resistor and including a breakdown protecting structure. Such breakdown occurs in an input transistor for receiving input data when an excess reverse voltage is applied across the emitter and base of the input transistor. The breakdown protection structure preferably includes a constant-voltage regulating device which can always clamp the level of a reference voltage VBB to a suitable level higher than a low voltage VEE of a power source by the value of a constant voltage. The reference voltage VBB is usually applied to the base of another transistor which should be coupled, at respective emitters, with the input transistor by the representative emitters.
申请公布号 DE3174856(D1) 申请公布日期 1986.07.24
申请号 DE19813174856 申请日期 1981.12.18
申请人 FUJITSU LIMITED 发明人 EMORI, SHINJI
分类号 H03K19/00;H03K19/003;H03K19/086;(IPC1-7):H03K19/003;H03K17/08 主分类号 H03K19/00
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