| 摘要 |
PURPOSE:To easily prevent the generation of a latch-up phenomenon by a method wherein an N<+> type contact region is arranged on the semiconductor substrate located between the source region of two transistors. CONSTITUTION:An N<+> type first contact region 11 is provided between MOS transistors 5 and 10. As a result, most of the parasitic current coming from an NPN transistor 15 is absorbed by the first contact region 11, almost no parasitic current runs between the base emitters of a PNP transistor 14, and also the holding loop generated by the internal resistance of a semiconductor substrate 1 is not formed. Also, as the first contact region 11 and a source region 2 are connected by a vapor-deposited aluminum electrode layer 33, para sitic resistance is not generated, and a holding looping is not formed at all. Accordingly, the PNP transistor 14 is not turned ON, and the strength of latch-up is increased. |
