发明名称 MEMORY CIRCUIT
摘要 <p>PURPOSE:To heighten reading speed by making the length of the gate of a transistor for balancing bit line short. CONSTITUTION:The gate length L of a P channel type transistor Q103 for balancing bit line is made shorter than other P channel type transistors. When the gate length L is made shorter, subthreshold current I0 increases. In the case where the gate length L is made short until I0 (leak current of high resistance load) and IR become nearly the same, memory cell data are broken by subthreshold current I0 of the transistor Q103 when the word line Xj is high level. Accordingly, subthreshold current I0 is selected to 1/20 of leak current IR of high resistance load. Supposing that the gate length L in this case is LB, subthreshold current I0 of the P channel type transistor Q103 for balancing bit line is 1/20 of IR. Accordingly, absolute value of threshold value voltage of the transistor Q103 becomes smaller than other transistors, and balancing operation of bit line is made easy correspondingly.</p>
申请公布号 JPS61162892(A) 申请公布日期 1986.07.23
申请号 JP19850002378 申请日期 1985.01.10
申请人 NEC CORP 发明人 KOBAYASHI YASUO
分类号 G11C11/41;G11C11/34 主分类号 G11C11/41
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