Integrated circuits incorporating a self-testing capability.

摘要

An integrated circuit having a built-in self test design, the integrated circuit including a combinatorial logic circuit (CLB), a first register means (BN) coupled to an output of the combinatorial logic circuit (CLB) and a feedback path (14) via which output signals from the first register means (BN) are fed back to an input of the combinatorial logic circuit (CLB). The present invention provides a multiplexer (M) coupled between the first register means (BN) and the feedback path (14), and second register means (BT) responsive to a signal which is originated to initiate a test function for feeding test signals via the multiplexer (M) and the feedback path (14) to the input of the combinatorial logic circuit (CLB)..