| 摘要 |
PURPOSE:To obtain a pulse generating circuit constituted of a simple circuit requiring only one signal from a delay circuit and an address especially with less constituting circuits by constituting the titled circuit of the delay circuit, the 1st and 2nd load elements, the 1st inverter circuit and 2nd inverter circuit. CONSTITUTION:The delay circuit D21 inputting the 1st signal SG1 generated from an address circuit and generating the 2nd signal SG2, the 1st and 2nd load elements R21, R22 one terminal of which are connected to a power supply 1, and the 1st inverter circuit comprising the 1st MISFETQ21 whose source is connected to common, whose drain is connected to the other end of the 1st load element R21, to the gate of which the 1st signal SG1 is inputted and the 2nd MISFETQ22 whose source and drain are connected in parallel with the 1st MISFETQ21 and to the gate of which the 2nd signal SG2 is inputted, are provided. Moreover, the 2nd inverter circuit comprising the 3rd MISFETQ23, the 4th MISFETQ24 and the 5th MISFETQ25 is provided. When there is a change in the logical level of an address input signal, a one-shot pulse is generated at an output contact N18. |
