| 摘要 |
PURPOSE:To make it possible to couple a CPU to a low-speed peripheral LSI which is operated with clocks having a frequency lower than that of operating clocks of the CPU, by using a wait signal to extend the operation cycle of the CPU. CONSTITUTION:A CPU1 and a peripheral LSI3 are couple by an interface circuit 2. This interface circuit 2 consists of three parts 2a-2c. The first interface circuit 2a divides the frequency of c clocks outputted from a clock oscillating circuit 4 by 2. These frequency-divided clock 8 are outputted to the inside of the interface circuit 2 and the peripheral LSI3. The second interface circuit 2b outputs a wait signal 6 only at the timing, when the signal 6 is required for the peripheral LSI3, by a control signal 5 from the CPU1. The third interface circuit 2c corrects the timing of the control signal 5 from the CPU1 and outputs a control signal 9 for peripheral LSI. |
