| 摘要 |
In a data processor for handling data comprising words of n-bits, a plurality of (n+m)-bit registers is provided for use as general purpose and address expansion registers, and effective addresss of (n+m)-bits are generated by adding addresses having n bits and provided in the instructions with the (n+m)-bit content of registers designated by the instructions. Thus, a data processor can be designed so as to have an expandable address bit length and flexible addressing with little additional hardware.
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