| 摘要 |
PURPOSE:To form a high speed A/D converting circuit as a structure suitable for a monolithic integrated circuit by relaxing the requirements of the accuracy of an internal A/D converter constituting a serial/parallel A/D converter and combining a capacitor array. CONSTITUTION:A 3-bit parallel A/D converter is constituted by voltage comparators CP0-CP7, resistors R0-R8 and a decoder 1. A voltage corresponding to a code by the minimum resolution voltage to the output code of an A/D converter is substracted from an input voltage of the A/D converter and the substracted voltage is amplified by 2N<-1> times, where N-bit is the resolution of the A/D converter by using switches SWS0-S7 controlled by an output of the CP0-CP7 and capable of switching over between a signal input terminal and ground or a reference potential 1VR, capacitors C0-C7 of the same capacitance and an SWSF. The output of the amplifier A1 is added to the output of the 1st A/D converter corresponding to the weight of the 2nd parallel A/D converter comprising resistors R10-R18, CP10-CP17 and a decoder 2.
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