| 摘要 |
PURPOSE:To shorten a pull-in time in a costas loop type synchronous detecting circuit by constituting said circuit so that an output of a multiplier for receiving an output of the first and the second phase detectors, and an output of a clock regenerator have no correlation. CONSTITUTION:A multiplier 8 multiplies output signals of a COS phase detector 4 and an SIN phase detector 6 and feeds them to a phase comparator 12. On the other hand, an IF receiving signal of an input side 2 is inputted directly to a delay detector 24 and demodulated, a demodulated signal is led out to a clock regenerator 26, and in the regenerator 26, a regenerated clock signal Vbit(t) is led out to the phase comparator 12. The phase comparator 12 multiplies said input signal and extracts a phase error contained in the IF receiving signal. In this way, the regenerator 26 comes to have no correlation to the phase detectors 4, 6 and the multiplier 8, and demodulated data required for regenerating a clock is inputted from the delay detector 24. Therefore, the time for securing the output Vbit(t) is determined only by a pull-in time of the regenerator 26, and the pull-in time becomes the sum of each pull-in time of Vx(t) and Vbit(t). |
