| 摘要 |
PURPOSE:To cope with its large capacity easily at a high speed by a combination of an asynchronous system packet switching circuit and a synchronizing system line switching circuit by constituting a titled system so that a packet switching circuit part of plural nodes uses a synchronizing bit position of a PCM frame as a time by taking synchronization to a time division multiplex transmission line interface. CONSTITUTION:Each node 30 is constituted of a loop access controlling circuit 31, a circuit switching device part 32, and a packet switching device part 33. This multiplexing system has an asynchronous oscillator to a transmission line 1, and also can take a timing buffer of a one bit portion of a synchronizing bit position at every one frame (193 bits), therefore, an oscillator of low accuracy can be used. A circuit 33A is constituted of the same interface as the circuit switching device, knows the synchronizing bit position by receiving a frame synchronizing signal from the controlling circuit 31, eliminates (n) pieces of data of that position, and brings data of (n)X192 bits to multiplex separation. In this way, it is unnecessary to provide an oscillator synchronized with a loop transmission line, an elastic buffer delay time of the data is small, and it can be transferred continuously so as to be asynchronous to all bits.
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