| 摘要 |
PURPOSE:To attain wire without provision of an externally mounted delay circuit by setting optionally a delay value of a RAM write control signal and a delay value of a RAM input data in a chip accessing a RAM. CONSTITUTION:When a WEi is inputted to a delay circuit (2)12 in a RAM write controller 7, a 2m-bit data delayed by 2m kinds of different delay values is outputted, and a multiplexer (1)13 uses an output of an m-bit mode setting register 1 as a decoder signal to select one bit among output data of a delay circuit (1)12 and output it as a WE signal. Similarly, when an input data control signal is inputted to a delay circuit (2)15, a 2n-bit data delayed by 2n kinds of different delay values is outputted, a multiplexer (2)16 uses an output of an n-bit mode setting register (2)14 a a decode signal to select one bit among output data of the delay circuit (2)15 and output a delay input data control signal. A j-bit input data written in the RAM is synchronized at a synchronizing circuit 17 by using the delay input data control signal to output a j-bit DATAIN.
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