| 摘要 |
PURPOSE:To enable to omit the mask-matching process for electrode formation and to enable to adopt a planing process by a method wherein a part of the semiconductor substrate, where is located between the anode and cathode electrodes on the substrate, is covered with implantation stoppig layers, ions are implaned in the substrate using the implantation stopping layers as implantation masks and the implanted regions are made into insulator regions. CONSTITUTION:A silicon nitride Si3N4 layer 24 is adhered on the whole surface of a substrate 21, whereon electrodes 23 ar formed, and after that, a resist 25 is adhered on the whole surface ofthe substrate 21 and a part of the resist 25, where is located between the source and drain electrodes, is left by performing a patterning on the resist 25. Then, after a dry etching is performed on the Si3N4 layer 24 with carbon tetrafluoride using the resist 25 as a mask, 0<+> ions ar implanted using the Au/AuGe layer 23, the Si3N4 layer 24 and the resist 25 is implantation masks. Then, the ion implanted regions, insu- lator regions 26 and 27, are formed and the resist 25 is removed. After that, the Si3N4 layer 24is removed, a silicon dioxide layer 28 is adhered on the whole surface of the substrate, an opening is provided on a part of the substrate surface, where is located between the source and the drain, by performing a patterning on the silicon dioxide layer 28, an aluminum A1 electrode 29 is adhered and the FET is completed. |
