| 摘要 |
PURPOSE:To decrease number of check bits by providing (n+1) sets of check bit storage cells to 2n-set of information bit storage cells connected to word lines so as to detect and correct an error of a 1-bit information bit storage cell connected to the same word line. CONSTITUTION:The 2n-set of cells are selected at the same time in response to an X direction address 13. The (n+1) sets of check bit storage cells connected to the same word lines as well as the information bit storage cells are selected in response to the X direction address 13 in this case. Thus, read information is latched to (2n+n+1) sets of sense amplifiers in total. Then 1-bit input information Din15 to be written in a Y direction address 14 and an information bit memory cell array 11 is inputted next. Thus, new input information is written in a cell in the information bit memory cell array 11, and the 1st check bit generating circuit 16 writes new check bit information to a check bit memory cell array 12.
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