| 摘要 |
<p>PURPOSE:To reduce the access time by adopting the constitution that a potential on a data line connected to an input terminal of a main sense amplifier is clamped to a prescribed potential at write period. CONSTITUTION:An output of an AND gate 5 is fed to a gate of FETs8, 9, 10 in a pre-sense amplifier 1 via an AND gate 15 being an activation inhibiting means. That is, the output of the AND gate 5 is fed to a control input terminal of switches 3, 4 in a write circuit 2 and one input terminal of the AND gate 15. A control signal R/W being at a low level at write is fed to the other input terminal of the AND gate 15. The output of the AND gate 15 is a gate input to the FETs 8, 9, 10. Further, each drain of FEHs 17, 18 being components of a clamp circuit 16 is connected to datalines D1, D2. The sources of FETs 17, 18 are connected to common. A control signal R/W being at a high level at write is fed to gates of the FETs 17, 18.</p> |
