| 摘要 |
PURPOSE:To confirm mounting of each unit to facilitate coping with extension of a system and to reduce the number of specially provided circuits by providing each unit with a NAND gate and fixing the level of one input. CONSTITUTION:An information processing part 14 and peripheral units 11-1-11-8 are connected by a data bus 15, an address bus 16, a control bus 17, and a detection control line 13. Individual units are provided with NAND gates 12-1-12-8, and one input of each NAND gate is fixed to the high level and is logical '1', and the other input is connected to the control line 13, and outputs of NAND gates are connected to data line inverted D0-D7 in the bus 15. A decoder 144 generates the timing, when mounting of each unit is confirmed, by an instruction from a CPU141 and gives logical '1' to the control line 13. If each unit is mounted, logical '1' is outputted to the corresponding data line from its NAND gate. The CPU reads data on the data bus to confirm the mounting state of each unit. |
