| 摘要 |
PURPOSE:To obtain an error output proportional to the difference between an input frequency and a discrimination frequency, by switching the input clocks within the discriminating range of a discriminating counter to keep the gain at a fixed level. CONSTITUTION:A frequency generator (FG) signal S1 is supplied to a timing signal generating circuit 1 and a discriminating counter, i.e., an (n+m)-bit binary counter 5 is preset and then counted down. Thus the 1st decoder 6 detects an m-bit all-zero detection signal S7, and a clock switching circuit 12 is switched for output of a clock signal S2. Then the 2nd decoder 11 detects the 1st clock switch signal S16 and the signal S2 is delivered from the circuit 12. Then the 2nd clock switch signal S17 is detected and a clock signal 12 is delivered from the circuit 12. Thus the gain is kept at a fixed level at a place near a reference frequency for discrimination.
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