| 摘要 |
PURPOSE:To efficiently attain the assembly of bits by sequentially storing in the shift register the information obtained by logical operation of flag bits indicating the state of the results of the operation. CONSTITUTION:ti, xi are inputted at terminals 5-1 and 5-2 of a parallel arithme tic unit 5 respectively, which then outputs a (b) s-bit of flag bits. A combinatorial circuit 6 selects a code bit s from these these b number of flag bits. The circuit 6 then performs subtraction between ti, and xi, the bit-s being equal to '1' when ti<xi. The bits-s is introduced into the lowermost place of a left bit shift register 7 where 1 bit shifting has occurred. These operations can be performed by one step and, by repetition of these operations, one-word data is obtained in the register 7. In case of overflow of the results of substraction, the bit-s is inverted and stored in the register 7. In such a manner, the correct value is found.
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